Helion: CuteDSL and TPU Backends for Heterogeneous Hardware, and Why It Suits Agents

PyTorch Conference North America 2026

Oct 20, 2026 · 11:45–12:10 · Timezone not confirmed

Helion is a Python DSL that raises kernel authoring above languages like CUDA and Triton: you describe a kernel at a high level, and a compiler and autotuner generate the device code. This talk introduces two new compiler backends. The motivation is hardware heterogeneity and performance. Accelerators are diverging, and reaching state-of-the-art performance on each one normally means hand-writing kernels in that vendor's low-level language. The new backends lower a Helion kernel through CuteDSL for recent NVIDIA GPUs and through Pallas for TPUs. The same source targets different hardware without giving up that performance or rewriting per vendor. The second half covers code generation by LLM agents. Because Helion sits above the languages it compiles to, a kernel takes fewer tokens to express and offers less surface area for mistakes, and the autotuner handles the performance tuning that agents do poorly. We cover where this holds up and where it doesn't.

Session status: scheduled

Room: 210BF

Track: Kernel Engineering

Level: Intermediate

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In person · San Jose Convention Center, San Jose, California, United States

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